1. Field of the Invention
The present invention relates to a signal transmission technique for transmitting signals at high speed between LSI chips or between elements or circuit blocks in an LSI chip, and between circuit boards or cabinets. More particularly, the present invention relates to a buffer circuit device for distributing a high-speed clock signal or outputting a high-speed data signal.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories), and other semiconductor devices such as processors and switching LSIs. The improvements in the performance of semiconductor memory devices, processors, and the like have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between a DRAM and a processor (i.e., between LSIS), for example, has been widening year by year and, in recent years, this speed gap has been becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, with increasing integration and increasing size of semiconductor chips, the speed of signal transmission between elements or circuit blocks within a chip is becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset is also becoming a factor limiting the overall performance of the system.
By the way, various kinds of clock, data, and the like signals are output through a buffer (buffer circuit device) so as to be transmitted between circuit blocks or LSI chips or cabinets. Especially, differential signals have been transmitted through a differential buffer along with high-speed and low voltage (small signal amplitude) in recent years. However, the common mode voltage of the differential signals output from the buffer and the common mode voltage necessary for a circuit (next-stage circuit) receiving the output signals of the buffer are frequently different. In such a case, an input sensitivity of the next-stage circuit may be reduced so that high-speed signal transmission may not be realized.
The prior art and its associated problems will be described in detail later with reference to relevant drawings.